Work Location:Qingdao,China

Responsibilities:

Seeking a IP Design Verification Engineer to join the IP Development team dealing with complex Communication ICs. In this role, you will focus on the following:

∙ Develop detailed test and coverage plans based on the micro‐architecture

∙ Develop verification methodology suitable for the IP, ensuring a scalable and portable environment

∙ Develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage

∙ Develop verification plans for all features under your care

∙ Execute verification plans, including design bring‐up, DV environment bring‐up, regression enabling all features under your care, and debug of the test failures.

∙ Develop block, IP and SoC level test‐benches

∙ Track and report DV progress using a variety of metrics, including bugs and coverage.

∙ Develop mixed‐signal simulation environment, and work closely with analog team to ensure overall bug‐free mixed‐signal design

Qualifications：

∙ Master’s/ Bachelor’s degree in electrical/Electronic/Computer Engineering

∙ 0‐5+ years’ experience in IP design verification

∙ Advanced knowledge of SystemVerilog and UVM

∙ Experience developing scalable and portable test‐benches

∙ Experience with verification methodologies and tools such as simulators, waveform viewers, build/run automation, coverage collection, gate level simulations

∙ Experience with mixed signal verification methodology for IPs such as PHYs, PLLs etc.

∙ In lieu of UVM knowledge, C/C++ experienced level knowledge

∙ Excellent knowledge of one of the scripting languages: Python, Perl, TCL

∙ Knowledge of formal verification methodology