Work Location：Qingdao,China

Position: IC Design Engineer

Key Qualifications：

∙ 3+ years of hands‐on experience in ASIC design flow

∙ Proven track record of high performance designs in high volume production for low power applications

∙ Knowledge and experience in MAC or PHY layer of wired/wireless communication system are highly desirable

∙ Solid background in SoC architecture including Bus fabric of APB/AHB/AXI/Wishbond/SPI, Power management with multiple power domains, Clock and reset trees, RF and analog controls, IO control and muxing

∙ Experience in ASIC design front end flows – Lint, CDC, STA, LEC

∙ Knowledge of Ultra‐Wideband(UWB) technology is a plus

∙ SoC top‐level integration experience and system architecture knowledge are a plus

∙ Proficiency in scripting languages (Shell and Perl desirable, Python skills are a plus)

∙ Self‐starter, highly motivated, highly organized, and schedule driven is a must

∙ Excellent communication and ability to work well in a team

Description：

∙ Microarchitecture definition

∙ Writing design specification, HW/FW programming guideline and other documents

∙ IP integration, RTL logic design and verification support

∙ Running front end tools to ensure lint‐free and CDC/RDC clean design

∙ Synthesis and timing constraints

∙ Power analysis and optimization

∙ Collaboration with system and software team to ensure functionality, performance, and power efficiency

∙ Develop and maintain methodology/flow/checks for own design

Education & Experience：

PhD/MSEE desired, BSEE required with equivalent years of experience