Work Location:Qingdao,China

Responsibilities：

Seeking a IP Design Engineer to join the IP Development team dealing with complex Communication ICs. In this role, you will focus on the following:

∙ Deliver complex digital control blocks, meeting schedule, area, power and performance targets

∙ Collaborate in developing precise design specifications for digital control blocks

∙ Implement FSM’s and other control logic in System Verilog

∙ Collaborate with managers and program managers to track progress and gauge tapeout readiness

∙ Work with DV teams to create verification plans

∙ Work with silicon validation team in developing lab validation and qualification plans

∙ Work with test team in developing implementation plans for ATE test programs

Qualifications:

∙ Master’s/ Bachelor’s degree in electrical/Electronic/Computer Engineering

∙ 0‐5+ years’ experience in developing digital IP’s for SoC’s or mixed signal IC’s

∙ Proven track record shipping quality designs on schedule

∙ Experience with synthesis and static timing tools

∙ Expertise in Clock Domain Crossing design and verification techniques

∙ Experience with power estimation tools and techniques

∙ Solid understanding of low power design techniques, including clock and power gating

∙ Familiarity with UPF based power intent specification and power verification

∙ Some familiarity with mix‐signal ASIC design and asynchronous analog / digital interfaces is helpful, but not required