Work Location：Qingdao,China

Responsibilities:

Seeking a DFT Engineer to join the SoC DfT team dealing with complex Communication ICs. In this role, you will focus on the following:

∙ Deliver structural Test Patterns (Scan/MBIST/iJTAG) for communication ICs

∙ Implement and verify DFT (Design For Test) schemes

∙ Implement techniques to test digital logic using Scan Compression, Stuck‐at, Transition and Path‐Delay fault models

∙ Achieve target Structural Test Coverage of the logic, memories and Mixed‐Signal IPs

∙ Pre‐Silicon and Post‐Silicon verification of Test Patterns

∙ Diagnose and debug the pattern failures on ATE to root cause the problem

∙ Responsible for implementing techniques to Optimize Test Time, Dynamic IR drop in scan shift and Yield improvement

∙ Work closely with Design Team and Product Engineering Teams to quickly resolve issues and meet high volume production schedule

Qualifications:

∙ Master’s/ Bachelor’s degree in electrical/Electronic/Computer Engineering

∙ 0‐5+ years’ experience in DFT and ATPG

∙ Good understanding of Digital Design and ASIC design flow

∙ Knowledge in VHDL/Verilog and IEEE 1149.1 standard

∙ Basic understanding of VLSI testing / fault models / DFT

∙ Knowledge of Perl / Shell Scripting is a plus

∙ Self‐motivated and a strong team‐player

∙ Strong analytical and problem‐solving skills

∙ Ability to learn new tools and technologies