Work Location：Qingdao,China

Salary : 20-40kRMB/ month*15months

Responsibilities：

1.Verify the design and implementation at the module / subsystem / chip level;

2.Determine the scope of validation according to the specification and develop validation plan/objectives3.Test platform development using random validation method (UVM, e. g.), test case development;

4.Build a reusable verification platform and develop a verification IP

5.The FPGA prototype validation is supported

6.Late simulations were performed using gate-level netlist.

7.Support for pre- / post-in-silico testing

Requirements:

1.Bachelor, master's degree in microelectronics, electronic engineering or related majors;

2.Familiar with verilog / System-Verilog / UVM;

3.Familiar with EDA tools (Modelsim, NC-sim, VCS, verdi);

4.Experience in low-power design and verification of large-scale digital circuits

5.Experience in scripting languages such as Perl / Python;

6.Familiar with 2G / 3G / 4G / 5G baseband architecture, ARM, AHB architecture is preferred;

7.Familiar with high-speed peripheral interface (PCIE/USB/ MIPI/I2C) is preferred;

8.Good English reading, communication ability and writing foundation.