Annual salary: 180,000-270,000 RMB/ year

Work Location: Qingdao, China

Job Responsibilities:

1. Complete the implementation of the module from algorithm/protocol to architecture;

2. Complete the RTL implementation and related verification of the module;

3. Complete PPA (Performance, Power, Area) optimization of the module;

4. Participate in algorithm/protocol/architecture evaluation and optimization;

5. Participate in module FPGA verification and chip debugging;

6. Participate in technical direction planning and solution evaluation.

Qualifications:

1, communication engineering, electronic engineering and other related master degree graduates;

2. Proficient in Verilog coding, capable of analyzing and designing complex digital logic and sequential circuit;

3. Experience in algorithm or processor IP or FPGA development is preferred