Work Location:Qingdao,China

Responsibilities:

Seeking a SoC Layout Physical Synthesis Engineer to join the SoC Physical Design team dealing with complex Communication ICs. In this role, you will focus on the following:

∙ Toplevel and block physical design partitioning

∙ All aspects of physical implementation, including floor‐planning, physical synthesis, clock‐tree synthesis, parasitic extraction

∙ IO ring design and bump implementation, meeting ESD, EMI and SSO requirements

∙ Implementation of Low power layout methodology (multiple switchable power domains, level shifter…)

∙ Execute static and dynamic drop, ramp up analysis using Redhawk

∙ Perform static timing analysis to handle complex timing closure.

∙ Work with other design engineer in Synthesis, Design for Testability, STA/timing closure and Equivalent checks to resolve issues.

Qualifications：

∙ Master’s/Bachelor’s Degree in Electrical/Electronics Engineering with an emphasis in IC design

∙ Experience with complex Low Power SOC is a plus

∙ Good experience with Synopsys implementation tool (DC, ICC2, Fusion Compiler), experience with Cadence implementation tool is a plus

∙ Experience in Mentor Verification tool, Calibre

∙ Experience in Redhawk

∙ Proficient in TCL code, python knowledge is a plus

∙ Able to work in a multi‐site, multi‐function team with a strong drive to excel

∙ Good written and communication skills