ASIC Verification Engineer(SSD)

Salary: 25-50kRMB/ month *14 months

Work Location:Qingdao,China

 

Responsibility Description

1. Responsible for making chip/module verification plans with high coverage;

2. Use SystemVerilog and UVM validation methodology for module and full chip function verification 3. Performance analysis and verification by simulation, FPGA and Emulator:

4. Perform post-simulation work with time sequence;

5. Provide test machine test vector for chip test engineer,

6. Use firmware code (C language) in SOC chip for chip test

7. Help FPGA engineers to build and adjust the FPGA verification environment of the chip/module

 

Requirements:

1. More than two years of experience in ASIC verification

2. Proficient in Systemverilog, Verilog language

3. Proficient in using validation methodologies, such as UVM, VMM;

4. Understand the CDV overlay dynamic random validation methodology, and can use random methodology to complete module level or system level validation

 

Skills Required:

UVM/OVM, SoC, digital verification